In the design of semiconductor devices, it is often advantageous (if not necessary) to monitor the behavior of some physical property of such device to characterize and thus determine whether a particular physical implementation is superior to another implementation. A substantial amount of research and effort is invested and undertaken by design and process engineers simply to create better, simpler, and more accurate test vehicles for observing the characteristics of a proposed design. The monitoring of device behavior and characteristics is done in a variety of ways, and one common method practiced today includes the use of test structures which are used either (or sometimes both) in the design and manufacturing of the devices in question. These test structures are usually implemented directly on the same substrate as the device under investigation, and are configured to be more easily accessible for measuring the property of interest.
An example of this is the threshold voltage of a Flash memory cell. This voltage is widely considered as the most critical parameter in determining the memory state that is being stored by the cell. The threshold voltage is controlled by the amount of charge that is placed on the floating gate of the Flash memory cell. In other words, this voltage is a direct function of the amount of charge stored within a particular cell. During the operation of the memory cells in an array, the floating gate for a given cell can inadvertently gain or lose charge. This unintentional charge gain or charge loss can change the memory state of the cell and become a cause of reliability failure in the Flash memory array. It is crucial to have a good monitor of this behavior for a large array of memory cells in a given Flash memory technology. As is also apparent, as the number of memory cells increases for a particular device, the expected variations between poor charge storing devices (leaky bits) and poor charge discharging devices (stubborn bits) are going to increase. For this reason, a testing mechanism which leads to more tightly controlled charge distribution populations is highly useful.
The most straightforward method to evaluate the charge-gain/charge-loss behavior of a device is to monitor the threshold voltage of each cell in the large memory array. This is often not convenient since it involves the use of a fully functional circuit onboard the device with all the proper decoding to address and access each individual cell in the memory array. However, this solution is not extremely practical from a functional or manufacturing perspective. It is substantially more useful for the population characteristics to be observed prior to the release of such device for use, and some manufacturing test procedures are known in the art for monitoring the devices as they are manufactured in a fabrication facility. Even this approach, however, is non-optimal, and for that reason, some degree of device behavior is both simulated and tested during the design phase of a particular flash cell, so that the charge population distribution of a particular physical cell implementation can be measured and controlled before full scale manufacturing is undertaken using such implementation.
Accordingly, it has become common in the industry to try and monitor the charge-gain/charge-loss behavior to evaluate the feasibility and reliability of an unproven Flash technology, prior to committing the design of a full functional circuit. In previous test structures of this type, an array of Flash EPROM memory cells are all connected together to provide a simple way of evaluating the behavior of the memory cell population. One drawback of this approach is that it is often capable of only evaluating the charge loss behavior of the memory array. The monitor of the charge gain behavior still has to resort to the use of a full functional memory array circuit. In such contexts, while it has been hitherto impossible, it would be very desirable to have a simple test structure capable of monitoring both the charge gain and charge loss behavior, without the use of full functional circuit.
FIG. 1 illustrates a test structure in the prior art that is capable of only monitoring the charge loss behavior. This structure typically consists of many cells (100, 101, 102, etc.) with a shared gate 100a, shared drain 100b, and shared source 100c. If all the cells are fixed at a same threshold voltage, the sub-threshold characteristics of the array will be equivalent to the sub-threshold characteristics of a single cell having a size equal to the total aggregate width of all the cells in the array. FIG. 2A illustrates an approximate graphical depiction of the sub-threshold behavior of an array with all the cells fixed at the same threshold voltage. (It should be noted that the Y-axis on the curve is in logarithmic scale.)
As is to be expected as a consequence of normal manufacturing variations, however, in the population of cells there will be cells having slightly different floating gate charge retention characteristics. This is inevitable given typical semiconductor processes which result in slightly different floating gate sizes, thicknesses, coupling to source/drains, etc. Thus, it is expected that there will be some random distribution (rather than a fixed or completely uniform distribution) of cell charge characteristics, with some being below a target charge retention characteristic, and some being above such target.
Accordingly, if a single cell in the test array experiences significant charge loss and results in a lower threshold voltage, the sub-threshold characteristics of the array will exhibit a different behavior than that expected for a completely uniform distribution. FIG. 2B illustrates a situation where a small number of cells are leaky (i.e., they have lost some charge) which results in a lower threshold voltage for such cells. These cells conduct current at a lower gate voltage V.sub.L before the main array begins to conduct current at a target gate voltage V.sub.target. The resulting sub-threshold characteristics will show a kink in the overall I-V curve, as illustrated in FIG. 2B. An observation of the heavy solid line of FIG. 2B, therefore, permits designers and manufacturers of flash cells to see and directly observe the size of this population, and study their characteristics, so that improvements (i.e., adaptations and refinements) can be made to the cell structure, or to the cell manufacturing process.
Through such improvements, of course, the cell populations should become more uniform and thus result in improved performance of devices utilizing such structures and processes. This is because the more uniform the distribution of cell charge populations (i.e., the more each cell is made to be identical to every other cell in the array) the more likely it is that various electrical operations occurring during the normal use of such cells in actual devices (such as erase and program) are going to be implemented correctly and successfully for each cell in the array.
In examining the solid line portion of the graph in FIG. 2B, however, it is apparent that users of such test structures are only able to glean information from one segment of the defective cell population. If, for example, some of the cells in this test structure array start to gain charge on their respective floating gate (as would be expected again as a result of manufacturing variations or as a result of defects and damage caused by operational stress), it will result in these cells having higher threshold voltages. These cells will start conduction at a higher gate voltage V.sub.H than the rest of the population. As shown in FIG. 2B, however, their contribution to the characteristics will not be noticed. This is because by the time these cells start to conduct a very small amount of subthreshold current, the rest of the population together, having a lower threshold voltage, will be conducting a current that is at least a few orders of magnitude higher than these cells. Thus, the charge gain behavior of cell populations in a Flash memory array cannot be observed using this kind of traditional test structure. This is true even though it is conceivable that the cell charge retention characteristics of a particular structure and process implementation may tend to result in a larger relative population of charge gainers versus charge losers.
Accordingly, a design that appears otherwise acceptable based on observations of prior art test structures may in fact have substantial charge gain defects that would go undetected. What is needed is an extension of the test structure to include the capability of evaluating the charge gain behavior, so that the true properties of various cell designs and processing techniques can be more accurately determined.